Communication stations such as, e.g., laptop computers; handheld devices like mobile phones, personal digital assistants (PDA) and the like; personal computers (PC) and the like, include components such as transmitters and receivers whose operating parameters are adjustable to compensate for variations in operating parameters such as signal transmission requirements, received signal strength and the like.
Typically, a log function generator module is employed whose output of an approximated logarithmic function corresponds, inter alia, to an estimation of received signal strength indication (RSSI). The log function generator module may approximate the logarithmic function by first determining the amplitude of each received signal and/or signal component and by subsequent conversion of the measured amplitude into a power level value by, e.g., suitable piecewise approximation.
However, estimating the RSSI is difficult in direct conversion receivers, which are receivers that include only one nixing stage and directly convert received radio frequency (RF) signals to baseband signals. The difficulty in estimating the RSSI arises when a frequency offset is present, i.e., when the local oscillation of the receiver does not match the local oscillation of the transmitting component. Thus, the abovementioned log function approximation(s) are not suitable for direct conversion receivers. Moreover, such approximation(s) are time-consuming and therefore decrease the operational reliability of the communication stations. Correspondingly, power consumption in a communication station employing a log function generator module performing said approximation(s) is inefficient. Efficient power consumption is of particular importance in portable, typically battery-powered communication stations because of the limited availability of power in these communication stations.
Turning now to FIG. 1, a log function generator module 1000 is schematically shown, which is adapted to approximate a logarithm of the root-mean-square (RMS) of the power for a plurality of signals. The log function generator module 1000 employs an SDLA architecture adapted to receive a plurality of signals. For exemplary purposes only, the plurality of signals is hereinafter referred to as signals Sin1 and Sin2.
Respective squaring modules 1400a and 1400b, which may be implemented by squaring circuits, square the signals Sin1 and Sin2. The purpose of the squaring signals is to substantially eliminate negative values in signals Sin1 and Sin2.
Upon performing squaring of respective signals Sin1 and Sin2, said signals may be summed up by adder 1500. The resulting signal Sres is then successively amplified by amplifiers 1200a-e. In order to obtain at the output of module 1000 a signal that substantially corresponds to the function Log(sqrt(Sin1^2+Sin2^2)), piecewise-linear approximation is performed by summing the signals at the substantially equally weighted taps 1100a-e. More specifically, piecewise-linear approximation may be accomplished by first limiting the signals at the outputs of the substantially equal amplifiers 1200a-e with limiters 1300a-e, respectively. The signals at the output of limiters 1300a-e may then be summed up by adders 1600a-d. The output of the last adder 1600d substantially corresponds to the Log(sqrt(Sin1^2+Sin2^2)). It is to be understood that module 1000 may include other SDLA architectures known in the art. For example, a single adder may sum up all the signals at the outputs of limiters 1300a-e. 
The SDIA architecture of module 1000 suffers, inter alia, from the following drawbacks: Signals Sin1 and Sin2 may each have a wide dynamic range, and with today's integrated circuit (IC) technology, it is not very feasible to design squaring circuits that are accurate enough to be able to process signals that have wide dynamic ranges.
The single-ended configuration of the output of adder 1500 renders the output of adder 1500 prone to DC mismatch, which may limit the dynamic range of the signal Sres. In consequence, adder 1500, and squaring modules 1400a and 1400b may have to be calibrated.
Signals such as Sin1 and Sin2 might suffer from static direct current (DC) offset. Since the squaring of signals (e.g., Sin1 and Sin2) is a non-linear function, the squared signals may have DC components that are undistinguishable from the static DC offset. In consequence, squaring renders the removal of static DC offset impossible. Therefore, static DC offset of the signals should be eliminated before said signals enter squaring modules 1400a and 1400b. Hence, additional circuitry may be needed before squaring modules 1400a and 1400b. 
The signals at the output of squarer modules 1400a and 1400b will have frequency components that are substantially double the frequency components incorporated in Sin1 and Sin2 Therefore, any signal processing stage subsequent to squarer modules 1400a and 1400b must be performed at a relatively high speed. Correspondingly, power consumption of subsequent signal processing stages is increased. The following equation schematically demonstrates how squaring of a signal of interest such as, e.g., A+Bsin(ωt) effects DC components as well as double frequency components:
            [              A        +                  B          ⁢                                          ⁢                      sin            ⁡                          (                              ω                ⁢                                                                  ⁢                t                            )                                          ]        2    =                    A        2            +              AB        ⁢                                  ⁢                  sin          ⁡                      (                          ω              ⁢                                                          ⁢              t                        )                              +                        B          2                ⁢                              sin            2                    ⁡                      (                          ω              ⁢                                                          ⁢              t                        )                                =                  A        2            +              AB        ⁢                                  ⁢                  sin          ⁡                      (                          ω              ⁢                                                          ⁢              t                        )                              +                        1          2                ⁢                  B          2                    +                        1          2                ⁢                  B          2                ⁢                  cos          ⁡                      (                          2              ⁢              ω              ⁢                                                          ⁢              t                        )                              wherein “A” and “B” represent the DC offset and the amplitude of the signal of interest, respectively, and wherein. “ω” is the angular frequency and “t” the time in seconds of said signal of interest, respectively. While the DC components A2 and 0.5 B2 can be eliminated, there is no practical way to eliminate the second component, which may mix with other signals at a frequency of ω/2, hence generating an error with respect to the required signal.
The said SDLA architecture may be employed for each communication link separately such that an alternative power estimation can be obtained. However, the alternative power estimation generates a final signal that corresponds to a logarithmic function of the form log(Sin1)+log(Sin2). The final signal largely depends on the properties of signals Sin1 and Sin2. Hence, employing the SDLA architecture for each communication link separately renders the alternative power estimation prone to significant errors.
Several attempts have been made so far that partly try to solve the abovementioned problems.
U.S. Pat. No. 7,130,601, which is incorporated by reference in its entirety herein, discloses determination of a received signal strength indication in a direct conversion receiver. The determination begins at a given time, a 1.sup.st value to be the larger of the in-phase component of the received signal and the quadrature component of the received signal. The direct conversion received then determines a 2. sup.nd value at the given time to be the smaller of the in-phase component of the received signal and the quadrature component of the received signal. As such, at a given time, the I .sup.st and 2. sup.nd values correspond to the greater and lesser of the in-phase component and quadrature component, respectively. Having obtained these values, the direct conversion receiver then determines the received signal strength indication based on the 1. sup.st value, the 2. sup.nd value and an offset value. The offset value provides a scaling of the RSSI value based on the range of the RSSI values. However, the received signal strength is determined by relying on the fact that the signals are correlated.
U.S. Pat. No. 3,858,036, which is incorporated by reference in its entirety herein, discloses a method that compares two signals that indicate two values, which are compared to produce a signal depending on the relative magnitudes of the values. The signal representing the relative magnitudes controls a scaler which divides the lesser of the by values by two and the greater, by one. The resulting quotients are summed in an adder. However, the two signals are not converted into a logarithmic scale.
U.S. Pat. No. 5,603,112, which is incorporated by reference in its entirety herein, discloses calculating received signal strength in a radio by hardware, which scales the absolute value of components of the received signal in a linear fashion by using two scaling factors. However, the received signal strength is determined by relying on the fact that components of the signal are correlated to each other.
U.S. Pat. No. 4,531,235, which is incorporated by reference in its entirety herein, discloses in one embodiment a diversity signal strength indicator for transmission site selection in a cellular-like mobile radio system to produce an output strength indication signal that is proportional to the logarithm of the average strength of two diversity input signals. The two input diversity signals are time-multiplexed together to form a composite signal, and a log amplifier/envelope detector then produces an intermediate log signal, which is proportional to the logarithm of the envelope of the composite signal. The intermediate log signal is then operated on by a peak detector to produce a peak intermediate log signal, which is then passed through a low pass filter to produce an output strength detection signal proportional to the average of the intermediate log signal and thus proportional to the logarithin of the average strength of the diversity input signal. In another embodiment, the time-multiplexed composite signal is first detected and then passed through a squaring module, a low pass filter and then a log amplifier to produce an output indicator circuit proportional to the logarithm of the average strength of the input diversity signals.
U.S. Pat. No. 5,523,875, which is incorporated by reference in its entirety herein, discloses an AGC for use in a multichannel RF system using fiber optic links. The circuit samples the power levels from a number of attenuated RF signals simultaneously and adjusts the gain in all of the channels by the amount required to keep the highest power channel below a predetermined power level.
Patent EP1143611, which is incorporated by reference in its entirety herein, discloses a system for automatic gain control to prevent input overload by precisely controlling the input level of a received, digitally modulated signal without using a variable gain amplifier.
U.S. patent application 6,917,791, which is incorporated by reference for all purposes as if fully set forth herein, discloses a polar loop transmitter circuit arrangement that comprises a circuit input, a circuit output and a controllable signal source. A modulator is coupled between the signal source and the output, whilst a first logarithmic amplifier is provided having its input coupled to the circuit input. A second logarithmic amplifier is also provided having its output coupled to the circuit output. An output of each logarithmic amplifier is coupled to a respective input of a comparator, and an output of the comparator is coupled to an input of the modulator. The logarithmic amplifiers can be successive detection logarithmic amplifiers, such amplifiers having an RF output which is amplitude limited and can be designed to have constant phase limited output.
Patent application 20040161030, which is incorporated by reference in its entirety herein, discloses an RSSI operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.
However, implementations of the above-referenced publications lack a system, a device, and/or method that allow determining the RSSI for a plurality of signals according to the baseband of the received signals.